| General information | |
|---|---|
| Launched | 2007 |
| Common manufacturer | |
| Performance | |
| Max. CPU clock rate | 600 MHz to 900 MHz |
| Physical specifications | |
| Cores |
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| Architecture and classification | |
| Technology node | 45 nm to 90 nm |
TILE64[1] is a VLIW ISA multicore processor manufactured by Tilera. It consists of a mesh network of 64 "tiles", where each tile houses a general purpose processor, cache, and a non-blocking router, which the tile uses to communicate with the other tiles on the processor.
The short-pipeline, in-order, three-issue cores implement a MIPS-inspired[2] VLIW instruction set. Each core has a register file and three functional units: two integer arithmetic logic units and a load–store unit. Each of the cores ("tile") has its own L1 and L2 caches plus an overall virtual L3 cache which is an aggregate of all the L2 caches.[3] A core is able to run a full operating system on its own or multiple cores can be used to run a symmetrical multi-processing operating system.
TILE64 has four DDR2 controllers, two 10-gigabit Ethernet interfaces, two four-lane PCIe interfaces, and a "flexible" input/output interface, which can be software-configured to handle a number of protocols. The processor is fabricated using a 90 nm process and runs at speeds of 600 to 900 MHz.
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According to CTO and co-founder Anant Agarwal, Tilera will target the chip at networking equipment and digital video markets where the demands for computing processing are high.[4]
Support for the TILE64 architecture was added to Linux kernel version 2.6.36[5] but was dropped in kernel version 4.16.[6] A non-official LLVM back-end for Tilera exists.[7]
References
edit- ^ Keckler, Stephen W.; Olukotun, Kunle; Peter Hofstee, H. (August 29, 2009). Multicore Processors and Systems - Google Books. Springer. ISBN 9781441902634.
- ^ "Compiler construction - What instruction set is used by Tilera microprocessors?".
- ^ Kingman, Henry (August 20, 2007). "Massively multicore processor runs Linux". linuxdevices.com.
{{cite news}}: CS1 maint: deprecated archival service (link) - ^ Boslet, Mark (August 20, 2007). "Start-up Tilera to Unveil 64-core chip". San Jose Mercury News. Archived from the original on November 12, 2007.
- ^ "Tilera architecture support". Kernel Newbies. October 20, 2010.
- ^ Simon Sharwood (April 3, 2018). "Linux 4.16 arrives, erases eight CPUs and keeps melting Meltdown". theregister.co.uk. Situation Publishing. Archived from the original on April 3, 2018. Retrieved April 3, 2018.
- ^ Tilera TILE64 Back-End For LLVM Published // Phoronix, September 6, 2012
External links
edit- Tilera website
- MIT startup raises multicore bar with new 64-core CPU
- Deprecated link at archive.today (archived 2013-01-19)
