📑 Table of Contents▼

In computing, an inter-processor interrupt (IPI), also known as a shoulder tap, is a special type of interrupt by which one processor may interrupt another processor in a multiprocessor system if the interrupting processor requires action from the other processor. Actions that might be requested include:

  • Flush memory management unit caches, such as translation lookaside buffers, on other processors when memory mappings are changed by one processor;
  • Stop when the system is being shut down by one processor.
  • Notify an alternate CPU of a malfunction for Alternate CPU Recovery (ACR).
  • Notify a processor that higher-priority work is available.
  • Notify a processor of work that cannot be done on all processors due to, e.g.,

Mechanism

edit

The M65MP option of OS/360 used the Direct Control feature of the S/360 to generate an interrupt on another processor; on S/370 and its successors, including z/Architecture, the SIGNAL PROCESSOR instruction provides a more formalized interface. The documentation for some IBM operating systems refers to this as a shoulder tap.

On IBM PC compatible computers that use the Advanced Programmable Interrupt Controller (APIC), IPI signaling is often performed using the APIC. When a CPU wishes to send an interrupt to another CPU, it stores the interrupt vector and the identifier of the target's local APIC in the Interrupt Command Register (ICR) of its own local APIC. A message is then sent via the APIC bus to the target's local APIC, which then issues a corresponding interrupt to its own CPU.

Examples

edit

Windows

edit

In a multiprocessor system running Microsoft Windows, a processor may interrupt another processor for the following reasons, in addition to the ones listed above:[3]

  1. queue a DISPATCH_LEVEL interrupt to schedule a particular thread for execution;
  2. kernel debugger breakpoint.

IPIs are given an IRQL of 29.[4]

See also

edit

References

edit
  1. ^ "Appendix F: Multiprocessing Extensions" (PDF). OS I/O Supervisor Logic - Release 21 - Program Number 360S-CI-505 (PDF). Program Logic. IBM. p. 271. GY28-6616-9. Retrieved August 28, 2022.
  2. ^ "AMD Technical Information Portal". docs.amd.com. Retrieved 2024-07-18.
  3. ^ "Inter Processor Interrupt usage". Stack Overflow. Retrieved 2024-07-18.
  4. ^ Matt (2002-04-28). "Understanding IRQL". Archived from the original on 2019-10-14. Retrieved 2014-12-06.
edit


Stub icon

This computer hardware article is a stub. You can help Wikipedia by adding missing information.

📚 Artikel Terkait di Wikipedia

Interrupt

computers, an interrupt is a request for the processor to interrupt currently executing code (when permitted), so that the event can be processed in a timely

Ralf Brown's Interrupt List

Ralf Brown's Interrupt List (aka RBIL, x86 Interrupt List, MS-DOS Interrupt List or INTER) is a comprehensive list of interrupts, calls, hooks, interfaces

Interrupt request

In a computer, an interrupt request (or IRQ) is a hardware signal sent to the processor that temporarily stops a running program and allows a special

Advanced Programmable Interrupt Controller

Mac G5s. Inter-processor interrupt (IPI) Interrupt Interrupt handler Interrupt latency Message Signaled Interrupts (MSI) Non-maskable interrupt (NMI) "MultiProcessor

Interrupt latency

increase processor utilization. Lastly, trying to reduce processor utilization may increase interrupt latency and decrease throughput. Minimum interrupt latency

Interrupt handler

needed] Interrupt vector table Advanced Programmable Interrupt Controller (APIC) Inter-processor interrupt (IPI) Interrupt latency Interrupts in 65xx

Programmable interrupt controller

notable PIC from Intel OpenPIC and IBM MPIC Inter-processor interrupt (IPI) Interrupt latency Non-maskable interrupt (NMI) IRQL (Windows) "Intel® 64 and IA-32

Non-maskable interrupt

Controller (APIC) Inter-processor interrupt (IPI) Interrupt Interrupt handler Interrupt latency Programmable Interrupt Controller (PIC) "Interrupt Levels". Retrieved