In computing, chaining is a technique used in vector processors in which vector registers generate interim results which can be used immediately, without additional memory references which reduce computational speed.[1] It is a vector equivalent of the register bypass for scalar operations.[2]

The chaining technique was first used by Seymour Cray in the 80 MHz Cray 1 supercomputer in 1976.[3]

References

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  1. ^ Richard M. Russell (January 1978). "The CRAY-1 Computer System". Communications of the ACM. 21 (1): 64. doi:10.1145/359327.359336.
  2. ^ Padua, David (2014-07-08). Encyclopedia of Parallel Computing. Springer Science & Business Media. ISBN 978-0-387-09766-4. Retrieved 2026-03-01.
  3. ^ M. O. Tokhi; Mohammad Alamgir Hossain (2003). Parallel computing for real-time signal processing and control. p. 201. ISBN 978-1-85233-599-1.


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