Operand forwarding (or data forwarding, register bypass) is an optimization in pipelined CPUs to limit performance deficits which occur due to pipeline stalls caused by data hazards.[1][2] A data hazard can lead to a pipeline stall when the current operation has to wait for the results of an earlier operation which has not yet finished.

It is very common that an instruction requires a value computed by the immediately preceding instruction. It may take a few clock cycles to write a result to the register file and then read it back for the subsequent instruction. To improve performance, the register file write/read is bypassed. The result of an instruction is forwarded directly to the execute stage of a subsequent instruction.

Example

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ADD A B C  #A=B+C
SUB D C A  #D=C-A

If these two assembly pseudocode instructions run in a pipeline, after fetching and decoding the second instruction, the pipeline stalls, waiting until the result of the addition is written and read.

Without operand forwarding
1 2 3 4 5 6 7 8
Fetch ADD Decode ADD Read Operands ADD Execute ADD Write result
Fetch SUB Decode SUB stall stall Read Operands SUB Execute SUB Write result
With operand forwarding
1 2 3 4 5 6 7
Fetch ADD Decode ADD Read Operands ADD Execute ADD Write result
Fetch SUB Decode SUB stall Read Operands SUB: use result from previous operation Execute SUB Write result

In some cases all stalls from such read-after-write data hazards can be completely eliminated by operand forwarding:[3][4][5]

With operand forwarding (enhanced)
1 2 3 4 5 6
Fetch ADD Decode ADD Read Operands ADD Execute ADD Write result
Fetch SUB Decode SUB Read Operands SUB: use result from previous operation Execute SUB Write result

Technical realization

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The CPU control unit must implement logic to detect dependencies where operand forwarding makes sense. A multiplexer can then be used to select the proper register or flip-flop to read the operand from.

See also

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References

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  1. ^ "CMSC 411 Lecture 19, Pipelining Data Forwarding". University of Maryland Baltimore County Computer Science and Electrical Engineering Department. Retrieved 2020-01-22.
  2. ^ "High performance computing, Notes of class 11". hpc.serc.iisc.ernet.in. September 2000. Archived from the original on 2013-12-27. Retrieved 2014-02-08.
  3. ^ Gurpur M. Prabhu. "Computer Architecture Tutorial". Sections "Forwarding". and "Data Hazard Classification".
  4. ^ Dr. Orion Lawlor. "Pipelining, Pipeline Stalls, and Operand Forwarding".
  5. ^ Larry Snyder. "Pipeline Review".
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📚 Artikel Terkait di Wikipedia

Hazard (computer architecture)

to deal with hazards, including pipeline stalls/pipeline bubbling, operand forwarding, and in the case of out-of-order execution, the scoreboarding method

Forwarding

email message onward to another email address Operand forwarding in an instruction pipeline Packet forwarding, the relaying of packets from one network segment

Arithmetic logic unit

units (GPUs). The inputs to an ALU are the data to be operated on, called operands, and a code indicating the operation to be performed (opcode); the ALU's

Memory-mapped I/O and port-mapped I/O

instructions that perform an ALU operation directly on a memory operand (loading an operand from a memory location, storing the result to a memory location

Pipeline (computing)

fetch. They are related to the technologies of superscalar execution, operand forwarding, speculative execution and out-of-order execution. Graphics pipelines

Software Guard Extensions

architecture Others Execution Instruction pipelining Pipeline stall Operand forwarding Classic RISC pipeline Hazards Data dependency Structural Control False

Translation lookaside buffer

architecture Others Execution Instruction pipelining Pipeline stall Operand forwarding Classic RISC pipeline Hazards Data dependency Structural Control False

Adder (electronics)

{\displaystyle C_{in}} ; A {\displaystyle A} and B {\displaystyle B} are the operands, and C i n {\displaystyle C_{in}} is a bit carried in from the previous